The present invention relates to a dual layer dopant diffusion barrier for use in III-V semiconductor structures.
One typical structure employed in optoelectronic devices is the p-i-n (PIN) structure. In a typical PIN structure, an intrinsic layer is disposed between a p-type layer and a n-type layer, forming a heterostructure device. The intrinsic layer has a larger index of refraction than the p and n layers resulting in a natural waveguide. Furthermore, the energy band discontinuities in the conduction and valence bands in the PIN structure facilitate carrier confinement within the active layer. In short, the PIN structure is well suited for a variety of emitting and detecting optoelectronic device applications.
One material that is often used in optoelectronics devices is indium phosphide (InP). In a PIN structure employing InP, a p-type layer is often fabricated by introducing zinc as a dopant. While zinc is a suitable dopant for forming p-type layer, zinc can readily diffuse due to the higher temperature achieved during the growth of InP. Diffusion into the active (intrinsic layer in a PINstructure) layer can occur resulting in the undesired doping of the active layer. This can have deleterious effects. For example, in a laser, intra-band transitions can occur, resulting in optical losses and reduced output power. Furthermore, the unintentional doping of the active layer can result in a shift in the emitted wavelength of an emitter. In applications where the PIN structure is used as an electro-absorptive modulator, zinc dopants in the active layer can change the absorption edge thereby degrading the extinction ratio.
One typical InP based structure used often in optoelectronic devices is a mesa structure having current blocking layers on either side of the mesa which provide transverse optical and carrier confinement. In many structures, one or more of the current blocking layers is iron doped indium phosphide (InP(Fe)). Unfortunately, inter-diffusion of p-dopants from the p-type layer and iron from the semi-insulating InP(Fe) layer is a common occurrence. This inter-diffusion may have detrimental effects on device characteristics. For example, the diffusion of the p-type dopants can readily result in leakage current in the device, and the inter-diffusion of the iron into the p-type layer results in its becoming more resistive. Accordingly, it is desirable to have a barrier layer to prevent the inter-diffusion.
An n-InP layer can be used as a dopant barrier layer. This type of barrier layer can be used to prevent dopant diffusion out of the p-cladding layer and into the active layer of a PIN device. Moreover, the n-InP layer can be used to prevent inter-diffusion of iron dopants and p-type dopants in a buried mesa structure device.
In the former case, where the n-InP layer is used to prevent diffusion of p-type dopants from the p-type layer, the n-type InP layer is disposed between the p-type layer and the active layer of the PIN device. While the n-InP layer prevents p-type dopants diffusion, it unfortunately forms an undesired pn junction is formed in the p-type layer. This parasitic pn junction may degrade device performance. Clearly, this is an undesired side affect of the use of an n-type InP diffusion blocking layer.
In the latter case, where the n-type in P diffusion barrier layer is used along the side of the mesa to prevent inter-diffusion of iron and p-type dopants, a relatively high concentration of n-type dopants (on the order to 1018 atoms/cm3) must be used to prevent p-type diffusion. Moreover, to ensure appropriate blocking of the dopants, it is necessary to make this layer relatively thick. Accordingly, a parasitic pn junction is established between the p-type cladding layer and n-type dopant diffusion blocking layer. This can cause an undesired current leakage path. Moreover, the disposition of the n-type diffusion barrier layer between the p-type cladding layer and the current blocking layer to prevent inter-diffusion can result in an increased parasitic capacitance. This can have deleterious effects on devices. This is particularly problematic in devices such as electro-absorptive modulators, lasers and digital devices in general as it adversely impacts device speed.
Accordingly, what is needed is a dopant diffusion barrier layer which successfully blocks diffusion of dopants, while not introducing parasitic elements to the device.
A multi-layer dopant diffusion barrier layer is disposed between a doped layer and another layer. The dual layer dopant diffusion barrier prevents inter-diffusion of dopants between the doped layer and the other layer. In one embodiment, this dual layer is used in conjunction with a dopant diffusion barrier layer that prevents diffusion of dopants from diffusing out of a doped layer into an intrinsic layer, without creating a p-n junction in the doped layer.